The field of invention relates generally to the fabrication of integrated circuits. More particularly, the invention relates to a process and apparatus for forming dielectric layers on a semiconductor substrate.
The fabrication of modern semiconductor devices includes forming multiple layers of conductive and dielectric materials on substrates. Formation of these layers occurs through various processes, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD) and the like.
The semiconductor industry strives to increase the number of semiconductor devices formed per unit area on the substrate. As a result, the feature size of the semiconductor devices continues to decrease. This has resulted in a doubling of the number of semiconductor devices present in a unit area every two years, referred to as Moore""s Law.
As the feature sizes associated with semiconductor devices decrease, the deleterious effects of the electrical characteristics of the materials from which the conductive and dielectric layers are formed increase. For example, the Resistance-Capacitance (RC) delay introduced by the aforementioned materials limits the operational speed of the semiconductor devices. As a result, there have been many attempts of alleviating RC delays in semiconductor devices.
Conventionally, RC delays are alleviated by employing materials having low dielectric constants, k. Many of the low dielectric materials, however, have properties that are incompatible with other materials employed to fabricate semiconductor devices or are incompatible with processes employed to fabricate the semiconductor devices. For example, adhesion to layers formed from a low dielectric constant material by adjacent layers is often poor, resulting in delamination. Additionally, layers formed from low dielectric materials are often structurally compromised by Chemical Mechanical Polishing (CMP) processes through erosion, as well as adsorption of CMP slurry chemicals. Etching processes often produce micro-trenches and rough surfaces in layers formed from materials having low dielectric constants, which is often unsuitable for subsequent photolithography processes. As a result, these materials are problematic to integrate into damascene fabrication processes.
Therefore, a need exists to provide improved techniques for producing semiconductor structures having layers formed from materials having low dielectric constants.